Double data rate (DDR) Oscilloscopes Bus and protocol testing

Challenges in the verification of a DDR memory interface

Name: Challenges in the verification of a DDR memory interface
Uploaded: 2019-03-25
Duration: 71 min 45 s
Description: DDR DRAM memory is expected to stay parallel for the next generation(s?) of memory. Verification and debugging of the interface is a difficult task. We look at the main design and debugging challenges and discuss best practices.

DDR DRAM memory is expected to stay parallel for the next generation(s?) of memory. Verification and debugging of the interface is a difficult task. We look at the main design and debugging challenges and discuss best practices.

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