High-speed serial pattern trigger software

Key facts

Analyse high-speed serial interfaces up to 16 Gbps
Hardware CDR is applicable to any input channel
Define single or dual-bit pattern up to 160 bits
Decoding of 8B/10B and 128B/132B symbols
Upgradable on any R&S®RTP Oscilloscope

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Brief description

The R&S®RTP-K140/141 options enable the high-speed serial pattern trigger function that can operate based on the extracted embedded clock of a serial signal. The R&S®RTP accomplishes this with hardware based clock data recovery (CDR) that supports a maximum nominal data rate of 8 Gbps or 16 Gbps, depending on the selected option.

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Features & benefits

Clock-data-recovery up to 16 Gbps

The R&S®RTP-K140/141 options enable a hardware based clock data recovery (CDR) that supports a maximum nominal data rate of 8 Gbps or 16 Gbps, depending on the selected software option. The CDR can use any of the four analog input channels. This function can be added as an upgrade at any time since the options are license key enabled.

**Setup of the hardware CDR** - Selected from predefined setting for various standards or work with the custom mode

High variety of trigger events

The high-speed serial pattern option of the R&S®RTP oscilloscope offers various trigger types:

single bit pattern (up to 160 bit)
dual bit pattern (logic OR of 2 pattern with max. 160 bit)
complex word (frame alignment and up to four bit pattern)
PRBS error (type 7, 9, 11, 15, 16, 17, 20, 23, 29, 31)
8b/10b symbols
128b/132b symbols

**Multiple pattern types** - The RTPs serial pattern trigger support various pattern types including bit pattern sequences, PRBS errors or line codes such as 8b/10b and 128b/132b.

Support of various line code

The R&S®RTP-K140/141 options support 8b/10b and 128b/132b symbols. The trigger aligns on specified words and triggers on a defined word sequence. This allows fast and easy debugging of protocol based highspeed interfaces such as USB or PCI Express.

**8b/10b symbol trigger for USB3.1 Gen1** - Trigger setup for USB3.1 Gen1 at 5 Gbps data rate. Alignment on a K28.5 word and a trigger condition consisting of five 8b/10b data words.

Signal integrity debugging

With the highspeed serial pattern trigger an data eye with the timing based on the embedded clock can be generated. For further signal integrity analysis, eye mask test and histogram functions are available.