3 Results
Debugging and verifying the DDR DRAM memory interface in a system design can be challenging. The R&S®RTP high-performance oscilloscope zone trigger is ideal for READ/WRITE separation as a basis for analyzing signal integrity.
06-Feb-2025
Compliance testing is essential to ensuring that dynamic random access memory (DRAM) signals meet the JEDEC specifications for parameters such as timing, slew rates and voltage levels. For system verification and debugging, eye diagram measurements are the most important tools for efficiently analyzing the signal integrity in any digital design. The specific nature of DDR requires a dedicated solution with a powerful read/write separation to get meaningful eye diagrams on the DDR data bus.
19-Feb-2019
When analyzing the signal integrity performance of DDR interfaces, separating read and write cycles has been a challenging task. Comprehensive trigger capabilities are required – especially when attempting to recreate the eye diagram in realtime.
26-Sep-2018